View M37736EHBXXXGP_5550719.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
l single power supply ...................................................... 5 v 10% l low power dissipation (at 25 mhz frequency) ............................................47.5 mw (typ.) l interrupts ............................................................ 19 types, 7 levels l multiple-function 16-bit timer ................................................. 5 + 3 l serial i/o (uart or clock synchronous) ..................................... 3 l 10-bit a-d converter ............................................ 8-channel inputs l 12-bit watchdog timer l programmable input/output, output (ports p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10)..........................84 l clock generating circuit ........................................ 2 circuits built-in application control devices for general commercial equipment such as office automation, office equipment, and others. control devices for general industrial equipment such as communication equipment, and others. note. do not use the windowed eprom version for mass production, because it is a tool for program development (for evaluation). 1 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs description the M37736EHBXXXGP is a single-chip microcomputer using the 7700 family core. this single-chip microcomputer has a cpu and a bus interface unit. the cpu is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. this microcomputer also includes a 32 khz oscillation circuit, in addition to the prom, ram, multiple-function timers, serial i/o, a-d converter, and others. in the M37736EHBXXXGP, as the multiplex method of the external bus, either of 2 types can be selected. the M37736EHBXXXGP has the same function as the m37736mhbxxxgp except that the built-in rom is prom. (refer to the basic function blocks description.) for program development, the m37736ehbgs with erasable rom that is housed in a windowed ceramic lcc is also provided. features l number of basic instructions .................................................. 103 l memory size prom ............................................. 124 kbytes ram ................................................ 3968 bytes l instruction execution time the fastest instruction at 25 mhz frequency ...................... 160 ns pin configuration (top view) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 ? p2 3 /a 19 /a 3 /d 3 ? p2 4 /a 20 /a 4 /d 4 ? p2 5 /a 21 /a 5 /d 5 ? p2 6 /a 22 /a 6 /d 6 ? p2 7 /a 23 /a 7 /d 7 ? p3 0 /r/w/wel ? p3 1 /bhe/weh ? p3 2 /ale ? p3 3 /hlda ? evl0 ? evl1 M37736EHBXXXGP v cc v ss ? e/rde ? x out ? x in ? reset ? bsel ? cnv ss ? byte ? p4 0 /hold ? p4 1 /rdy 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p8 6 /r x d 1 ? p8 5 /clk 1 ? p8 4 /cts 1 /rts 1 ? p8 3 /t x d 0 ? p8 2 /r x d 0 /clks 0 ? p8 1 /clk 0 ? p8 0 /cts 0 /rts 0 /clks 1 ? v cc av cc v ref ? av ss v ss p7 7 /an 7 /x cin ? p7 6 /an 6 /x cout ? p7 5 /an 5 /ad trg ? p7 4 /an 4 ? p7 3 /an 3 ? p7 2 /an 2 ? p7 1 /an 1 ? p7 0 /an 0 ? 75 74 73 72 71 80 79 78 77 76 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ? p9 2 /r x d 2 ? p9 3 /t x d 2 ? p9 4 ? p8 7 /t x d 1 ? p9 0 /cts 2 ? p9 1 /clk 2 ? p9 5 ? p9 6 ? p9 7 ? p0 0 /a 0 /cs 0 ? p0 1 /a 1 /cs 1 ? p0 2 /a 2 /cs 2 ? p0 3 /a 3 /cs 3 ? p0 4 /a 4 /cs 4 ? p0 5 /a 5 /rsmp ? p0 6 /a 6 /a 16 ? p0 7 /a 7 /a 17 ? p1 0 /a 8 /d 8 ? p1 1 /a 9 /d 9 ? p1 2 /a 10 /d 10 ? p1 3 /a 11 /d 11 ? p1 4 /a 12 /d 12 ? p1 5 /a 13 /d 13 ? p1 6 /a 14 /d 14 ? p1 7 /a 15 /d 15 ? p2 0 /a 16 /a 0 /d 0 ? p2 1 /a 17 /a 1 /d 1 ? p2 2 /a 18 /a 2 /d 2 p6 5 /tb0 in ? p6 7 /tb2 in / f sub ? p6 6 /tb1 in ? p6 4 /int 2 ? p6 3 /int 1 ? p6 2 /int 0 ? p6 1 /ta4 in ? p6 0 /ta4 out ? p5 7 /ta3 in ? p5 6 /ta3 out ? p5 5 /ta2 in ? p5 4 /ta2 out ? p5 3 /ta1 in ? p5 2 /ta1 out ? p5 1 /ta0 in ? p5 0 /ta0 out ? p10 7 /ki 3 ? p10 6 /ki 2 ? p10 5 /ki 1 ? p10 4 /ki 0 ? p10 3 ? p10 2 ? p10 1 ? p10 0 ? p4 7 ? p4 6 ? p4 5 ? 26 27 28 29 30 p4 4 ? p4 3 ? p4 2 / f 1 ? outline 100p6s-a
preliminary notice: this is not a final specification. some parametric limits are subject to change. 2 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs M37736EHBXXXGP block diagram ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? clock input x in clock output x out clock generating circuit timer ta4(16) ram 3968 bytes prom 124 kbytes timer ta3(16) timer ta2(16) timer ta1(16) p8(8) input/output port p8 p7(8) input/output port p7 x cin x cout p6(8) input/output port p6 p5(8) input/output port p5 p4(8) input/output port p4 p3(4) input/output port p3 p2(8) input/output port p2 p1(8) input/output port p1 p0(8) input/output port p0 timer ta0(16) watchdog timer timer tb2(16) timer tb1(16) timer tb0(16) uart2(9) uart1(9) uart0(9) a-d converter(10) instruction register(8) data buffer db h (8) data buffer db l (8) processor status register ps(11) direct page register dpr(16) stack pointer s(16) index register y(16) index register x(16) accumulator b(16) arithmetic logic unit(16) accumulator a(16) instruction queue buffer q 0 (8) instruction queue buffer q 1 (8) incrementer(24) program address register pa(24) data address register da(24) instruction queue buffer q 2 (8) program counter pc(16) incrementer/decrementer(24) program bank register pg(8) data bank register dt((8) input buffer register ib(16) address bus data bus(even) data bus(odd) x cin x cout enable output e reset input reset (0v) v ss (0v) av ss cnv ss av cc reference voltage input v ref bus method selection input bsel external data bus width selection input byte v cc ? ? ? ? ? ? ? ? ? p9(8) output port p9 ? ? ? ? ? ? ? ? ? p10(8) input/output port p10
3 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m67736ehbgs functions of M37736EHBXXXGP memory size input/output ports multi-function timers interrupts clock generating circuit input/output characteristic memory expansion 100-pin ceramic lcc (with a window) (100d0) parameter functions number of basic instructions 103 instruction execution time 160 ns (the fastest instruction at external clock 25 mhz frequency) prom 124 kbytes ram 3968 bytes p0 C p2, p4 C p8, p10 8-bit 5 9 p3 4-bit 5 1 output port p9 8-bit 5 1 ta0, ta1, ta2, ta3, ta4 16-bit 5 5 tb0, tb1, tb2 16-bit 5 3 serial i/o (uart or clock synchronous serial i/o) 5 3 a-d converter 10-bit 5 1 (8 channels) watchdog timer 12-bit 5 1 3 external types, 16 internal types each interrupt can be set to the priority level (0 C 7.) 2 circuits built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) supply voltage 5 v 10% power dissipation 47.5 mw (at external clock 25 mhz frequency) input/output voltage 5 v output current 5 ma external bus mode a; maximum 16 mbytes, external bus mode b; maximum 1 mbytes operating temperature range C20 to 85 c device structure cmos high-performance silicon gate process 100-pin plastic molded qfp (100p6s-a) package M37736EHBXXXGP m37736ehbgs
preliminary notice: this is not a final specification. some parametric limits are subject to change. 4 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs pin description x in clock input input bus method select input x out clock output output pin name input/output functions vcc, power source apply 5 v 10% to vcc and 0 v to vss. vss cnvss cnvss input input this pin controls the processor mode. connect to vss for the single-chip mode and the memory expansion mode, and to vcc for the microprocessor mode. _____ reset reset input input when l level is applied to this pin, the microcomputer enters the reset state. these are pins of main-clock generating circuit. connect a ceramic resonator or a quartz- crystal oscillator between x in and x out . when an external clock is used, the clock source should be connected to the x in pin, and the x out pin should be left open. _ e enable output output this pin functions as the enable signal output pin which indicates the access status in the internal bus. in the external bus mode b and the memory expansion mode or the microprocessor mode, ___ this pin output signal rde . byte external data input in the memory expansion mode or the microprocessor mode, this pin determines whether the bus width external data bus has an 8-bit width or a 16-bit width. the data bus has a 16-bit width when l selection input signal is input and an 8-bit width when h signal is input. bsel input in the memory expansion mode or the microprocessor mode, this pin determines the external bus mode. the bus mode becomes the external bus mode a when h signal is input, and the external bus mode b when l signal is input. avcc, analog power power source input pin for the a-d converter. externally connect avcc to vcc and avss to vss. avss source input v ref reference input this is reference voltage input pin for the a-d converter. voltage input p0 0 C p0 7 i/o port p0 i/o in the single-chip mode, port p0 becomes an 8-bit i/o port. an i/o direction register is available so that each pin can be programmed for input or output. these ports are in the input mode when reset. in the memory expansion mode or the microprocessor mode, these pins output address (a 0 C a 7 ) ___ ___ ____ at the external bus mode a, and these pins output signals cs 0 C cs 4 and rsmp, and addresses (a 16 , a 17 ) at the external bus mode b. p1 0 C p1 7 i/o port p1 i/o in the single-chip mode, these pins have the same functions as port p0. when the byte pin is set to l in the memory expansion mode or the microprocessor mode and external data bus has a 16-bit width, high-order data (d 8 C d 15 ) is input/output or an address (a 8 C a 15 ) is output. when the byte pin is h and an external data bus has an 8-bit width, only address (a 8 C a 15 ) is output. p2 0 C p2 7 i/o port p2 i/o in the single-chip mode, these pins have the same functions as port p0. in the memory expansion mode or the microprocessor mode, low-order data (d 0 C d 7 ) is input/output or an address is output. when using the external bus mode a, the address is a 16 C a 23 . when using the external bus mode b, the address is a 0 C a 7 . p3 0 C p3 3 i/o port p3 i/o in the single-chip mode, these pins have the same function as port p0. in the memory expansion __ ___ ____ mode or the microprocessor mode, r/ w , bhe , ale, and hlda signals are output at the external ___ ___ ____ bus mode a, and wel , weh , ale, and hlda signals are output at the external bus mode b. p4 0 C p4 7 i/o port p4 i/o in the single-chip mode, these pins have the same functions as port p0. in the memory expansion ____ ___ mode or the microprocessor mode, p4 0 , p4 1 and p4 2 become hold and rdy input pins, and a clock f 1 output pin, respectively. functions of the other pins are the same as in the single-chip mode. however, in the memory expansion mode, p4 2 can be selected as an i/o port. p5 0 C p5 7 i/o port p5 i/o in addition to having the same functions as port p0 in the single-chip mode, these pins also function as i/o pins for timers a0 to a3. p6 0 C p6 7 i/o port p6 i/o in addition to having the same functions as port p0 in the single-chip mode, these pins also ___ ___ function as i/o pins for timer a4, input pins for external interrupt input ( int 0 C int 2 ) and input pins for timers b0 to b2. p6 7 also functions as sub-clock f sub output pin. p7 0 C p7 7 i/o port p7 i/o in addition to having the same functions as port p0 in the single-chip mode, these pins function as input pins for a-d converter. additionally, p7 6 and p7 7 have the function as the output pin (x cout ) and the input pin (x cin ) of the sub-clock (32 khz) oscillation circuit, respectively. when p7 6 and p7 7 are used as the x cout and x cin pins, connect a resonator or an oscillator between the both. p8 0 C p8 7 i/o port p8 i/o in addition to having the same functions as port p0 in the single-chip mode, these pins also function as i/o pins for uart 0 and uart 1. p9 0 C p9 7 output port p9 output port p9 is an 8-bit i/o port. these ports are floating when reset. when writting to the port latch, these ports become the output mode. p9 0 C p9 3 also function as i/o port for uart 2. p10 0 C p10 7 i/o port p10 i/o in addition to having the same functions as port p0 in the single-chip mode, p10 4 C p10 7 also __ __ function as input pins for key input interrupt input ( ki 0 C ki 3 ). output these pins should be left open. evl0, evl1 CC
5 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m67736ehbgs input/output input input input input output output input input input i/o input input input input input input input input input input output pin description (eprom mode) functions supply 5v10% to v cc and 0v to v ss . connect to v pp when programming or verifing. connect to v pp when programming or verifing. connect to v ss . connect a ceramic resonator between x in and x out . keep open. connect av cc to v cc and av ss to v ss . connect to v ss . port p0 functions as the lower 8 bits address input (a 0 C a 7 ). port p1 functions as the higher 8 bits address input (a 8 C a 15 ). port p2 functions as the 8 bits data input/output (d 0 C d 7 ). p3 0 functions as the most significant bit address input (a 16 ). connect to v ss . connect to v ss . _____ ___ ___ p5 0 , p5 1, and p5 2 function as pgm , oe, and ce input pins respectively. connect p5 3 , p5 4 , p5 5, and p5 6 to v cc . connect p5 7 to v ss . connect to v ss . connect to v ss . connect to v ss . connect to v ss . connect to v ss . connect to v cc . keep open. pin v cc , v ss cnv ss byte _____ reset x in x out _ e av cc , av ss v ref p0 0 C p0 7 p1 0 C p1 7 p2 0 C p2 7 p3 0 p3 1 C p3 3 p4 0 C p4 7 p5 0 C p5 7 p6 0 C p6 7 p7 0 C p7 7 p8 0 C p8 7 p9 0 C p9 7 p10 0 C p10 7 bsel evl0, evl1 name power supply v pp input v pp input reset input clock input clock output enable output analog supply input reference voltage input address input (a 0 C a 7 ) address input (a 8 C a 15 ) data i/o (d 0 C d 7 ) address input (a 16 ) input port p3 input port p4 control signal input input port p6 input port p7 input port p8 input port p9 input port p10 _____ _____ basic function blocks the M37736EHBXXXGP has the same function as the m37736mhb xxxgp except that the built-in rom is prom. refer to the section on the m37736mhbxxxgp.
preliminary notice: this is not a final specification. some parametric limits are subject to change. 6 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs outline 100p6s-a eprom mode the M37736EHBXXXGP features an eprom mode in addition to _____ its normal modes. when the reset signal level is l, the chip automatically enters the eprom mode. table 1 list the correspondence between pins and figure 1 shows the pin connections in the eprom mode. the eprom mode is the 1m mode for the eprom that is equivalent to the m5m27c101k. when in the eprom mode, ports p0, p1, p2, p3 0 , p5 0 , p5 1 , p5 2 , cnv ss , and byte are used for the eprom (equivalent to the m5m27c101k). when in this mode, the built-in prom can be programmed or read from using these pins in the same way as with the m5m27c101k. this chip does not have device identifier mode, so that set the corresponding program algorithm. the program area should specify address 01000 16 C 1ffff 16 . connect the clock which is either ceramic resonator or external clock to x in pin and x out pin. table 1 pin function in eprom mode v cc v pp v ss address input data i/o ___ ce ___ oe _____ pgm m5m27c101k v cc v pp v ss a 0 C a 16 d 0 C d 7 ___ ce ___ oe _____ pgm M37736EHBXXXGP v cc cnv ss , byte v ss ports p0, p1, p3 0 port p2 p5 2 p5 1 p5 0 fig. 1 pin connection in eprom mode 1 p6 7 ? p6 6 ? p6 5 ? p6 4 ? p6 3 ? p6 2 ? p6 1 ? p6 0 ? p5 7 ? p5 6 ? p5 5 ? p5 4 ? p5 3 ? p5 2 ? p5 1 ? p5 0 ? p10 7 ? p10 6 ? p10 5 ? p10 4 ? p10 3 ? p10 2 ? p10 1 ? p10 0 ? p4 7 ? p4 6 ? p4 5 ? p4 4 ? p4 3 ? p4 2 ? p2 4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 25 26 28 29 30 52 51 ? p2 3 ? p2 2 53 ? p2 1 54 ? p2 0 55 ? p1 7 56 ? p1 6 57 ? p1 5 58 ? p1 4 59 ? p1 3 60 ? p1 2 61 ? p1 1 62 ? p1 0 63 ? p0 7 64 ? p0 6 65 ? p0 5 66 ? p0 4 67 ? p0 3 68 ? p0 2 69 ? p0 1 70 ? p0 0 71 ? p9 7 72 ? p9 6 73 ? p9 5 74 ? p9 4 75 ? p9 3 76 ? p9 2 77 ? p9 1 78 ? p9 0 79 ? p8 7 80 31 ? p4 1 ? p4 0 ? byte cnv ss ? bsel ? reset ? x in ? x out ? e v ss v cc ? evl1 ? evl0 ? p3 3 ? p3 2 ? p3 1 ? p3 0 ? p2 7 ? p2 6 ? p2 5 d 5 d 4 d 3 d 2 d 1 d 0 a 15 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 14 d 6 d 7 a 16 v ss v cc v pp p gm oe ce * * : connect to ceramic oscillation circuit. : it is used in the eprom mode. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 av ss p7 0 ? p7 1 ? p7 2 ? p7 3 ? p7 4 ? p7 5 ? p7 6 ? p7 7 ? v ss v ref ? av cc v cc p8 0 ? p8 1 ? p8 2 ? m37736ehbgp p8 3 ? p8 4 ? p8 5 ? p8 6 ? ? ?
7 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m67736ehbgs function in eprom mode 1m mode (equivalent to the m5m27c101k) reading ___ ___ to read the eprom, set the ce and oe pins to a l level. input the address of the data (a 0 C a 16 ) to be read, and the data will be output to the i/o pins d 0 C d 7 . the data i/o pins will be floating when either __ __ the ce or oe pins are in the h state. programming programming must be performed in 8 bits by a byte program. to ___ ___ program to the eprom, set the ce pin to a l level and the oe pin to a h level. the cpu will enter the programming mode when 12.5 v is applied to the v pp pin. the address to be programmed to is selected with pins a 0 C a 16 , and the data to be programmed is input to pins d 0 _____ C d 7 . set the pgm pin to a l level to being programming. erasing to erase data on this chip, use an ultraviolet light source with a 2537 angstrom wave length. the minimum radiation power necessary for erasing is 15 j/cm 2 . programming operation to program the m37733ehbxxxfp, first set v cc = 6 v, v pp = 12.5 v, and set the address to 01000 16 . apply a 0.2 ms programming pulse, check that the data can be read, and if it cannot be read ok, repeat the procedure, applying a 0.2 ms programming pulse and checking that the data can be read until it can be read ok. record the accumulated number of pulse applied (x) before the data can be read ok, and then write the data again, applying a further once this number of pulses (0.2 5 x ms). when this series of programming operations is complete, increment the address, and continue to repeat the procedure above until the last address has been reached. finally, when all addresses have been programmed, read with v cc = v pp = 5 v (or v cc = v pp = 5.5 v). table 2. i/o signal in each mode read-out output disable programming programming verify program disable v il v il v ih v il v il v ih v il v ih x v ih v il v ih x x x v il v ih v ih 5 v 5 v 5 v 12.5 v 12.5 v 12.5 v 5 v 5 v 5 v 6 v 6 v 6 v output floating floating input output floating ___ ce ___ oe _____ pgm v pp v cc data i/o mode pin note 1 : an x indicates either v il or v ih . programming operation (equivalent to the m5m27c101k) ac electrical characteristics (t a = 25 5 c, v cc = 6 v 0.25 v, v pp = 12.5 0.3 v, unless otherwise noted) address setup time ___ oe setup time data setup time address hold time data hold time output enable to output float delay v cc setup time v pp setup time _____ pgm pulse width _____ pgm over program pulse width ___ ce setup time __ data valid from oe s s s s s ns s s ms ms s ns t as t oes t ds t ah t dh t dfp t vcs t vps t pw t opw t ces t oe min. 2 2 2 0 2 0 2 2 0.19 0.19 2 typ. 0.2 max. 130 0.21 5.25 150 symbol parameter test conditions limits unit
preliminary notice: this is not a final specification. some parametric limits are subject to change. 8 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs t dfp t ah t dh t ds t as t vps t vcs t ces t pw t opw t oes t oe data set data output valid program verify v ih v il v ih /v oh v il /v ol v pp v cc v cc +1 v cc v ih v il v ih v il v ih v il address data v pp v cc ce pgm oe ac waveforms programming algorithm flow chart start addr=first location v cc =6.0 v v pp =12.5 v x=0 program one pulse of 0.2 ms x=x+1 x=25? verify byte last addr? v cc =v pp =*5.0 v device passed program pulse of 0.2x ms duration verify all byte fail fail device failed fail device failed yes pass yes increment addr no verify byte pass pass no *4.5 v v cc = v pp 5.5 v test conditions for a.c. characteristics input voltage : v il = 0.45 v, v ih = 2.4 v input rise and fall times (10 % C 90 %) : 20 ns reference voltage at timing measurement : input, output l = 0.8 v, h = 2 v
9 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs safety instructions (1) sunlight and fluorescent lamp contain light that can erase written information. when using in read mode, be sure to cover the transparent glass portion with a seal or other materials (ceramic package product). (2) mitsubishi electric corp. provides the seal for covering the transparent glass. take care that the seal does not touch the read pins (ceramic package product). (3) clean the transparent glass before erasing. fingers fat and paste disturb the passage of ultraviolet rays and may affect badly the erasure capability (ceramic package product). (4) a high voltage is used for programming. take care that over- voltage is not applied. take care especially at power on. (5) the programmable m37736ehbgp that is shipped in blank is also provided. for the m37736ehbgp, mitsubishi electric corp. does not perform prom programming test and screening following the assembly processes. to improve reliability after programming, performing programming and test according to the flow below before use is recommended. addressing modes the M37736EHBXXXGP has 28 powerful addressing modes. refer to the 7700 family software manual for the details. machine instruction list the M37736EHBXXXGP has 103 machine instructions. refer to the 7700 family software manual for the details. data required for prom ordering please send the following data for writing to prom. (1) M37736EHBXXXGP writing to prom order confirmation form (2) 100p6s mark specification form (3) rom data (eprom 3 sets) programming with prom programmer function check in target device verify test with prom programmer caution : never expose to 150 c exceeding 100 hours. screening (leave at 150 c for 40 hours) (caution)
preliminary notice: this is not a final specification. some parametric limits are subject to change. 10 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs absolute maximum ratings symbol parameter conditions ratings unit vcc power source voltage C0.3 to +7 v avcc analog power source voltage C0.3 to +7 v v i _____ input voltage reset , cnvss, byte C0.3 to +12(note) v input voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3, p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7, p8 0 C p8 7 , p9 0 C p9 2 , p10 0 C p10 7 , v ref , x in, bsel output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3, p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, _ p9 0 C p9 7 , p10 0 C p10 7 , x out , e p d power dissipation ta = 25 c 300 mw t opr operating temperature C20 to +85 c t stg storage temperature C40 to +150 c v i v o C0.3 to vcc + 0.3 v C0.3 to vcc + 0.3 v note. when the eprom is programmed, input voltage of pins cnvss and byte is 13 v respectively. notes 1. average output current is the average value of a 100 ms interval. 2. the sum of i ol(peak) for ports p0, p1, p2, p3, p8, and p9 must be 80 ma or less, the sum of i oh(peak) for ports p0, p1, p2, p3, p8, and p9 must be 80 ma or less, the sum of i ol(peak) for ports p4, p5, p6, p7, and p10 must be 100 ma or less, and the sum of i oh(peak) for ports p4, p5, p6, p7, and p10 must be 80 ma or less. 3. limits v ih and v il for x cin are applied when the sub clock external input selection bit = 1. 4. the maximum value of f(x in ) = 12.5 mhz when the main clock division selection bit = 1. limits min. typ. max. f(x in ) : operating 4.5 5.0 5.5 f(x in ) : stopped, f(x cin ) = 32.768 khz 2.7 5.5 avcc analog power source voltage vcc v vss power source voltage 0v avss analog power source voltage 0 v high-level input voltage p0 0 C p0 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , _____ p7 0 C p7 7 , p8 0 C p8 7 , p9 0 C p9 2 , p10 0 C p10 7 , x in , reset , cnvss, byte, bsel, x cin (note 3) high-level input voltage p1 0 C p1 7 , p2 0 C p2 7 (in single-chip mode) high-level input voltage p1 0 C p1 7 , p2 0 C p2 7 (in memory expansion mode and microprocessor mode) low-level input voltage p0 0 C p0 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , _____ p7 0 C p7 7 , p8 0 C p8 7 , p9 0 C p9 2 , p10 0 C p10 7 , x in , reset , cnvss, byte, bsel, x cin (note 3) low-level input voltage p1 0 C p1 7 , p2 0 C p2 7 (in single-chip mode) low-level input voltage p1 0 C p1 7 , p2 0 C p2 7 (in memory expansion mode and microprocessor mode) high-level peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, p9 0 C p9 7 , p10 0 C p10 7 high-level average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, p9 0 C p9 7 , p10 0 C p10 7 low-level peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 3 , p5 4 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, p9 0 C p9 7 , p10 4 C p10 7 low-level peak output current p4 4 C p4 7 , p10 0 C p10 3 low-level average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 3 , p5 4 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, p9 0 C p9 7 , p10 4 C p10 7 i ol(avg) low-level average output current p4 4 C p4 7 , p10 0 C p10 3 15 ma f(x in ) main-clock oscillation frequency (note 4) 25 mhz f(x cin) sub-clock oscillation frequency 32.768 50 khz unit symbol parameter v vcc power source voltage v ih v ih v ih v il v il v il i oh(peak) i oh(avg) i ol(peak) i ol(peak) i ol(avg) 0.8 vcc 0.8 vcc 0.5 vcc 0 0 0 vcc vcc vcc 0.2vcc 0.2vcc 0.16vcc C10 C5 10 20 5 v v v v v v ma ma ma ma ma recommended operating conditions (vcc = 5 v 10%, ta = C20 to +85 c, unless otherwise noted)
11 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m67736ehbgs limits min. typ. max. high-level output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, p9 0 C p9 7 , p10 0 C p10 7 high-level output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 3 i oh = C10 ma 3.1 i ch = C400 a 4.8 i oh = C10 ma 3.4 i oh = C400 a 4.8 low-level output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 3 , p4 0 C p4 3 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 5 , p8 0 C p8 7, p9 0 C p9 7 , p10 4 C p10 7 v ol low-level output voltage p4 4 C p4 7 , p10 0 C p10 3 i ol = 20 ma 2 v low-level output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 3 i ol = 10 ma 1.9 i ol = 2 ma 0.43 i ol = 10 ma 1.6 i ol = 2 ma 0.4 hysteresis ____ ___ hold , rdy , ta0 in C ta4 in , tb0 in C tb2 in , v t+ C v tC _______ _______ __________ ________ ________ ________ int 0 C int 2 , ad trg , cts 0 , cts 1 , cts 2 , clk 0 , 0.4 1 v _____ _____ clk 1 , clk 2 , ki 0 C ki 3 v t+ C v tC _____ hysteresis reset 0.2 0.5 v v t+ C v tC hysteresis x in 0.1 0.4 v v t+ C v tC hysteresis x cin (when external clock is input) 0.1 0.4 v high-level input current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , _____ p8 0 C p8 7 , p9 0 C p9 2 , p10 0 C p10 7 , x in , reset , cnvss, byte, bsel low-level input current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 , p6 1 , p6 5 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 , p9 0 C p9 2 , p10 0 C p10 3 , _____ x in, reset , cnvss, byte, bsel v i = 0 v, without a pull-up transistor v i = 0 v, with a pull-up transistor v ram ram hold voltage when clock is stopped. 2v unit electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) symbol parameter test conditions v v oh high-level output voltage _ e v oh high-level output voltage p3 0 C p3 2 v ol _ low-level output voltage e v ol low-level output voltage p3 0 C p3 2 v oh v ol i il low-level input current p10 4 C p10 7 , p6 2 C p6 4 i il i ih v oh v ol i oh = C400 a 4.7 v v v i ol = 2 ma 0.45 v v i ol = 10 ma 2 v v i = 0 v v i = 5 v a ma a a 5 C5 C1.0 C5 C0.5 C0.25 i oh = C10 ma 3 v
preliminary notice: this is not a final specification. some parametric limits are subject to change. 12 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs v cc = 5 v, f(x in ) = 25 mhz (square waveform), f(f 2 ) = 12.5 mhz, f(x cin ) = 32.768 khz, in operating (note 1) v cc = 5 v, f(x in ) = 25 mhz (square waveform), (f(f 2 ) = 1.5625 mhz), f(x cin ) = stopped, in operating (note 1) v cc = 5v, f(x in ) = 25 mhz (square waveform), f(x cin ) = 32.768 khz, when a wit instruction is executed (note 2) v cc = 5 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, in operating (note 3) v cc = 5 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, when a wit instruction is executed (note 4) ta = 25 c, when clock is stopped ta = 85 c, when clock is stopped electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to 85 c, unless otherwise noted) max. limits typ. unit min. test conditionssymbol parameter 9.5 1.3 10 50 5 20 2.6 19 100 10 1 ma ma a a a a a power source current i cc in single-chip mode, output pins are open, and other pins are v ss . notes 1. this applies when the main clock external input selection bit = 1, the main clock division selection bit = 0, and the signal output stop bit = 1. 2. this applies when the main clock external input selection bit = 1 and the system clock stop bit at wait state = 1. 3. this applies when cpu and the clock timer are operating with the sub clock (32.768 khz) selected as the system clock. 4. this applies when the x cout drivability selection bit = 0 and the system clock stop bit at wait state = 1. 20 limits min. typ. max. resolution v ref = v cc 10 bits absolute accuracy v ref = v cc 3 lsb r ladder ladder resistance v ref = v cc 10 25 k w t conv conversion time 9.44 s v ref reference voltage 2 v cc v v ia analog input voltage 0 v ref v symbol parameter test conditions unit aCd converter characteristics (v cc = av cc = 5 v, v ss = av ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note), unless otherwise noted) note. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz.
13 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m67736ehbgs limits min. max. t su(dCe) data input setup time (external bus mode a) 32 ns t su(dCrde) data input setup time (external bus mode b) 32 ns t su(rdyC f 1) ___ rdy input setup time 55 ns t su(holdC f 1) ____ hold input setup time 55 ns t h(eCd) data input hold time (external bus mode a) 0 ns t h(rdeCd) data input hold time (external bus mode b) 0 ns t h( f 1Crdy) ___ rdy input hold time 0ns t h( f 1Chold) ____ hold input hold time 0ns limits min. max. t su(p0dCe) port p0 input setup time 60 ns t su(p1dCe) port p1 input setup time 60 ns t su(p2d-e) port p2 input setup time 60 ns t su(p3dCe) port p3 input setup time 60 ns t su(p4dCe) port p4 input setup time 60 ns t su(p5dCe) port p5 input setup time 60 ns t su(p6dCe) port p6 input setup time 60 ns t su(p7dCe) port p7 input setup time 60 ns t su(p8dCe) port p8 input setup time 60 ns t su(p10dCe) port p10 input setup time 60 ns t h(eCp0d) port p0 input hold time 0ns t h(eCp1d) port p1 input hold time 0ns t h(eCp2d) port p2 input hold time 0ns t h(eCp3d) port p3 input hold time 0ns t h(eCp4d) port p4 input hold time 0ns t h(eCp5d) port p5 input hold time 0ns t h(eCp6d) port p6 input hold time 0ns t h(eCp7d) port p7 input hold time 0ns t h(eCp8d) port p8 input hold time 0ns t h(eCp10d) port p10 input hold time 0ns limits min. max. t c external clock input cycle time (note 3) 40 ns t w(h) external clock input high-level pulse width (note 4) 15 ns t w(l) external clock input low-level pulse width (note 4) 15 ns t r external clock rise time 8ns t f external clock fall time 8ns timing requirements (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted (note)) notes 1. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2. input signals rise/fall time must be 100 ns or less, unless otherwise noted. external clock input unit symbol parameter unit symbol parameter single-chip mode notes 3. when the main clock division selection bit = 1, the minimum value of tc = 80 ns. 4. when the main clock division selection bit = 1, values of tw (h) / tc and tw (l) / tc must be set to values from 0.45 through 0.55. unit symbol parameter memory expansion mode and microprocessor mode
preliminary notice: this is not a final specification. some parametric limits are subject to change. 14 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs limits min. max. t c(ta) tai in input cycle time 80 ns t w(tah) tai in input high-level pulse width 40 ns t w(tal) tai in input low-level pulse width 40 ns unit symbol parameter timer a input (count input in event counter mode) limits min. max. t c(ta) tai in input cycle time (note) 320 ns t w(tah) tai in input high-level pulse width (note) 160 ns t w(tal) tai in input low-level pulse width (note) 160 ns unit symbol parameter timer a input (gating input in timer mode) limits min. max. t c(ta) tai in input cycle time (note) 320 ns t w(tah) tai in input high-level pulse width 80 ns t w(tal) tai in input low-level pulse width 80 ns unit symbol parameter timer a input (external trigger input in one-shot pulse mode) limits min. max. t w(tah) tai in input high-level pulse width 80 ns t w(tal) tai in input low-level pulse width 80 ns unit symbol parameter timer a input (external trigger input in pulse width modulation mode) limits min. max. t c(up) tai out input cycle time 2000 ns t w(uph) tai out input high-level pulse width 1000 ns t w(upl) tai out input low-level pulse width 1000 ns t su(upCt in ) tai out input setup time 400 ns t h(t in Cup) tai out input hold time 400 ns unit symbol parameter timer a input (up-down input in event counter mode) unit symbol parameter timer a input (two-phase pulse input in event counter mode) limits min. max. t c(ta) taj input cycle time 800 ns t su(taj in Ctaj out ) taj in input setup time 200 ns t su(taj out Ctaj in ) taj out input setup time 200 ns note. limits change depending on f(x in ). refer to data formulas. note. limits change depending on f(x in ). refer to data formulas.
15 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m67736ehbgs limits min. max. t c(ad) ad trg input cycle time (minimum allowable trigger) 1000 ns t w(adl) ad trg input low-level pulse width 125 ns limits min. max. t c(ck) clk i input cycle time 200 ns t w(ckh) clk i input high-level pulse width 100 ns t w(ckl) clk i input low-level pulse width 100 ns t d(cCq) t x d i output delay time 80 ns t h(cCq) t x d i hold time 0ns t su(dCc) r x d i input setup time 30 ns t h(cCd) r x d i input hold time 90 ns limits min. max. t c(tb) tbi in input cycle time (one edge count) 80 ns t w(tbh) tbi in input high-level pulse width (one edge count) 40 ns t w(tbl) tbi in input low-level pulse width (one edge count) 40 ns t c(tb) tbi in input cycle time (both edges count) 160 ns t w(tbh) tbi in input high-level pulse width (both edges count) 80 ns t w(tbl) tbi in input low-level pulse width (both edges count) 80 ns unit symbol parameter timer b input (count input in event counter mode) limits min. max. t c(tb) tbi in input cycle time (note) 320 ns t w(tbh) tbi in input high-level pulse width (note) 160 ns t w(tbl) tbi in input low-level pulse width (note) 160 ns unit symbol parameter timer b input (pulse period measurement mode) limits min. max. t c(tb) tbi in input cycle time (note) 320 ns t w(tbh) tbi in input high-level pulse width (note) 160 ns t w(tbl) tbi in input low-level pulse width (note) 160 ns unit symbol parameter timer b input (pulse width measurement mode) limits min. max. t c(ad) __________ ad trg input cycle time (minimum allowable trigger) 1000 ns t w(adl) __________ ad trg input low-level pulse width 125 ns unit symbol parameter a-d trigger input unit symbol parameter serial i/o limits min. max. t w(inh) _______ int i input high-level pulse width 250 ns t w(inl) ______ int i input low-level pulse width 250 ns t w(kil) ____ ki i input low-level pulse width 250 ns unit symbol parameter limits min. max. t c(ck) clk i input cycle time 200 ns t w(ckh) clk i input high-level pulse width 100 ns t w(ckl) clk i input low-level pulse width 100 ns t d(cCq) t x d i output delay time 80 ns t h(cCq) t x d i hold time 0ns t su(dCc) r x d i input setup time 30 ns t h(cCd) r x d i input hold time 90 ns limits min. max. t c(tb) tbi in input cycle time (note) 320 ns t w(tbh) tbi in input high-level pulse width (note) 160 ns t w(tbl) tbi in input low-level pulse width (note) 160 ns unit symbol parameter timer b input (pulse width measurement mode) unit symbol parameter a-d trigger input unit symbol parameter serial i/o unit symbol parameter ______ ____ external interrupt int i input, key input interrupt ki i input note. limits change depending on f(x in ). refer to data formulas. note. limits change depending on f(x in ). refer to data formulas.
preliminary notice: this is not a final specification. some parametric limits are subject to change. 16 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs data formulas timer a input (gating input in timer mode) limits min. max. symbol parameter unit t c(ta) tai in input cycle time t w(tah) tai in input high-level pulse width t w ( tal ) tai in input low-level pulse width ns ns ns 8 5 10 9 2 f(f 2 ) timer a input (external trigger input in one-shot pulse mode) limits min. max. symbol parameter unit t c(ta) tai in input cycle time ns timer b input (in pulse period measurement mode or pulse width measurement mode) limits min. max. symbol parameter unit ns ns ns t c(tb) tbi in input cycle time t w(tbh) tbi in input high-level pulse width t w(tbl) tbi in input low-level pulse width 8 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) 8 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) note. f(f 2 ) represents the clock f 2 frequency. for the relation to the main clock and sub clock, refer to table 10 in data sheet m37736mhbxxxgp .
17 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m67736ehbgs limits min. max. t d(eCp0q) port p0 data output delay time 80 ns t d(eCp1q) port p1 data output delay time 80 ns t d(eCp2q) port p2 data output delay time 80 ns t d(eCp3q) port p3 data output delay time 80 ns t d(eCp4q) port p4 data output delay time 80 ns t d(eCp5q) port p5 data output delay time 80 ns t d(eCp6q) port p6 data output delay time 80 ns t d(eCp7q) port p7 data output delay time 80 ns t d(eCp8q) port p8 data output delay time 80 ns t d(eCp9q) port p9 data output delay time 80 ns t d(eCp10q) port p10 data output delay time 80 ns unit symbol parameter test conditions switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85c, f(x in ) = 25 mhz (note), unless otherwise noted) note. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. fig. 2 measuring circuit for ports p0 C p10 and f 1 fig. 2 p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 9 p10 f 1 e 50 pf
preliminary notice: this is not a final specification. some parametric limits are subject to change. 18 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs [external bus mode a] memory expansion mode and microprocessor mode (v cc = 5 v 10%, v ss = 0 v, ta = 25 c, f(x in ) = 25 mhz (note 1), unless otherwise noted) symbol parameter t d(eCdq) t h(eCdq) address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time limits wait mode min. max. test conditions unit 45 5 12 87 12 75 18 22 57 5 45 9 15 4 10 18 50 130 20 12 87 12 87 18 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t d(anCe) t d(aCe) t d(aleCe) t h(eCan) t w(ale) t su(aCale) t h(aleCa) t w(el) data output delay time data hold delay time _ e pulse width floating start delay time floating release delay time ___ bhe output delay time _ r/ w output delay time ___ bhe hold time _ r/ w hold time no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 (note 2) f 1 output delay time t pxz(eCdz) t pzx(eCdz) t d(bheCe) t d(r/wCe) t h(eCbhe) t h(eCr/w) t d(eC f 1 ) t d( f 1 Chlda) ____ hlda output delay time 018 50 notes 1. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2. no wait : wait bit = 1. wait 1 : the external memory area is accessed with wait bit = 0 and wait selection bit = 1. wait 0 : the external memory area is accessed with wait bit = 0 and wait selection bit = 0. fig. 2
19 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m67736ehbgs [external bus mode a] memory expansion mode and microprocessor mode bus timing data formulas (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (max., note), unless otherwise noted) address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time data output delay time data hold time _ e pulse width floating start delay time floating release delay time no wait wait 1 wait 0 45 5 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) ns ns ns ns ns ns ns ns ns ns no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 1 5 10 9 2 f(f 2 ) ns ns ns ns ns ns 9 4 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) ns ns 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) C 28 C 33 C 28 C 45 C 22 C 18 C 23 C 35 C 35 C 25 C 30 C 22 C 30 C 30 C 20 C 28 C 33 C 28 C 33 C 22 C 22 unit symbol parameter limits wait mode min. max. t d(anCe) t d(aCe) t h(eCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCe) t d(eCdq) t h(eCdq) t w(el) t pxz(eCdz) t pzx(eCdz) no wait wait 1 wait 0 ___ bhe output delay time _ r/ w output delay time t d(bheCe) t d(r/wCe) t h(eCbhe) t h(eCr/w) t d(eC f 1) f 1 output delay time _ r/ w hold time ___ bhe hold time 0 18 ns ns ns ns ns ns ns ns notes 1. this applies when the main-clock division selection bit = 0. 2. f(f 2 ) represents the clock f 2 frequency. for the relation to the main clock and sub clock, refer to table 10 in data sheet m37736mhbxxxgp .
preliminary notice: this is not a final specification. some parametric limits are subject to change. 20 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs [external bus mode b] memory expansion mode and microprocessor mode (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1), unless otherwise noted) symbol parameter chip-select output delay time chip-select hold time address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time data output delay time data hold delay time ___ ___ wel / weh pulse width floating start delay time floating release delay time ___ rde pulse width ____ rsmp output delay time ____ rsmp hold time f 1 output delay time ____ hlda output delay time limits wait mode min. max. test conditions t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) t d(anCwe) t d(anCrde) t d(aCwe) t d(aCrde) t h(weCan) t h(rdeCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCwe) t d(aleCrde) t d(weCdq) t h(weCdq) t w(we) t pxz(rdeCdz) t pzx(rdeCdz) t w(rde) t d(rsmpCwe) t d(rsmpCrde) t h( f 1 Crsmp) t d(weC f 1 ) t d(rdeC f 1 ) t d( f 1 Chlda) notes 1. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2. no wait : wait bit = 1. wait 1 : the external memory area is accessed with wait bit = 0 and wait selection bit = 1. wait 0 : the external memory area is accessed with wait bit = 0 and wait selection bit = 0. unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 45 5 18 50 12 87 4 12 87 12 75 18 22 57 5 45 9 15 4 10 18 50 130 20 48 128 10 0 0 (note 2) no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 fig.2
21 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m67736ehbgs [external bus mode b] memory expansion mode and microprocessor mode bus timing data formulas (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (max., note1), unless otherwise noted) 45 5 18 limits wait mode min. max. symbol parameter unit 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) ns ns no wait wait 1 wait 0 t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) t d(anCwe) t d(anCrde) t d(aCwe) t d(aCrde) t h(weCan) t h(rdeCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCwe) t d(aleCrde) t d(weCdq) t h(weCdq) t w(we) t pxz(rdeCdz) t pzx(rdeCdz) t w(rde) t d(rsmpCwe) t d(rsmpCrde) t h( f 1 Crsmp) t d(weC f 1 ) t d(rdeC f 1 ) ns4 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) ns ns ns ns ns ns ns ns ns ns no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 1 5 10 9 2 f(f 2 ) ns ns ns ns ns ns 9 4 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) ns ns 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) ns ns ns ns ns ns 0 0 chip-select output delay time chip-select hold time address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time data output delay time data hold time ___ ___ wel / weh pulse width floating start delay time floating release delay time ___ rde pulse width ____ rsmp output delay time ____ rsmp hold time f 1 output delay time C 28 C 33 C 28 C 45 C 22 C 18 C 23 C 35 C 35 C 25 C 30 C 22 C 30 C 30 C 20 C 32 C 32 C 30 C 28 C 33 notes 1. this applies when the main-clock division selection bit = 0. 2. f(f 2 ) represents the clock f 2 frequency. for the relation to the main clock and sub clock, refer to table 10 in data sheet m37736mhbxxxgp .
preliminary notice: this is not a final specification. some parametric limits are subject to change. 22 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs timing diagram t w(h) t d(e?iq) t d(e?2q) t d(e?3q) t d(e?4q) t d(e?5q) t d(e?6q) t d(e?7q) t d(e?8q) port pi output (i = 0 ?10) port pi input (i = 0 ?8, 10) port p1 output port p1 input port p2 output port p2 input port p3 output port p3 input e x in port p4 output port p4 input port p5 output port p5 input port p6 output port p6 input port p7 output port p7 input port p8 output port p8 input single-chip mode t su(pid?) t h(e?id) t d(e?1q) t r t f t w(l) t c t su(p1d?) t h(e?1d) t su(p2d?) t h(e?2d) t su(p3d?) t h(e?3d) t su(p4d?) t h(e?4d) t su(p5d?) t h(e?5d) t su(p6d?) t h(e?6d) t su(p7d?) t h(e?7d) t su(p8d?) t h(e?8d)
23 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m67736ehbgs tai in input tai out input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in ?p) t su(up? in ) tai out input (up-down input) tai in input (when count by falling) tai in input (when count by rising) in event count mode taj in input taj out input t c(ta) t su(taj in ?aj out ) t su(taj in ?aj out ) t su(taj out ?aj in ) t su(taj out ?aj in ) in event counter mode (when two-phase pulse input is selected) t c(tb) t w(tbh) t w(tbl) tbi in input
preliminary notice: this is not a final specification. some parametric limits are subject to change. 24 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(knl) t d(c?) t su(d?) t h(c?) t w(inh) ad trg input clk i txd i rxd i inti input kli input t h(c?)
25 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m67736ehbgs memory expansion mode and microprocessor mode (when wait bit = 1) ( when wait bit = 0) (when wait bit = 1 or 0 in common) test conditions ? v cc = 5 v 10% ? input timing voltage : v il = 1.0 v, v ih = 4.0 v ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v 1 rdy input 1 e or rde, wel, weh rdy input 1 hold input hlda output t su(rdyC 1 ) t h( 1 Crdy) t su(rdyC 1 ) t h( 1 Crdy) t su(holdC 1 ) t d( 1 Chlda) t h( 1 Chold) t d( 1 Chlda) e or rde, wel, weh f f f f f f f f f f f
preliminary notice: this is not a final specification. some parametric limits are subject to change. 26 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs f 1 t d(e- f 1) t d(an-e) t w(ale) t d(ale-e) t su(a-ale) t d(a-e) t d(e-dq) t h(ale-a) t d(bhe-e) t h(e-bhe) t d(r/w-e) t h(e-r/w) t h(e-dq) t pxz(e-dz) t su(d-e) t h(e-d) t pzx(e-dz) t h(e-an) t d(e- f 1) t w(el) t w(h) e an ale am/dm dm in bhe r/ w address address addressdata data address address address t f t r t c t w(l) test conditions v cc = 5 v 10% output timing voltage : v ol = 0.8 v, v oh = 2.0 v data input dm in : v il = 0.8 v, v ih = 2.5 v x in [external bus mode a] memory expansion mode and microprocessor mode (no wait : when wait bit = 1)
27 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m67736ehbgs t w(ale) t c address t w(l) t w(h) t f t r address address t d(e f 1 ) t d(an?) t d(ale?) t su(aale) t h(ale?) t d(a?) t d(e?q) t h(e?) t pzx(e?z) t h(e?he) t su(de) test conditions ?vcc = 5 v 10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input dm in : v il = 0.8 v, v ih = 2.5 v data address data t d(e f 1 ) address t pxz(e?z) t w(el) t h(e?n) t h(e?q) t h(e?/w) t d(r/w?) t d(bhe?) x in e an ale am/dm dm in bhe r /w f 1 [external bus mode a] memory expansion mode and microprocessor mode (wait 1 : the external area is accessed when wait bit = 0 and wait selection = 1.)
preliminary notice: this is not a final specification. some parametric limits are subject to change. 28 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs [external bus mode a] t h(ale?) t d(ale?) t d(e?q) t w(l) t w(h) t f t c t r memory expansion mode and microprocessor mode (wait 0 : the external memory area is accessed when wait bit = ??and wait selection bit = ??) x in f 1 address address address address data an ale am/dm dm in r /w t d(an?) t w(ale) t su(a?le) t h(e?q) t d(a?) t pxz(e?z) t pzx(e?z) t h(e?) t su(d?) addressdataaddress test conditions ?vcc = 5 v 10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input dm in : v il = 0.8 v, v ih = 2.5 v t d(e f 1 ) t d(e f 1 ) t d(r/w?) t h(e?/w) t w(el) t h(e?n) t d(bhe?) t h(e?he) e bhe
29 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m67736ehbgs [external bus mode b] memory expansion mode and microprocessor mode (no wait : when wait bit = 1) t w(we) t h(we Cdq) t w(l) t w(h) t f t r t c x in f 1 cs 0 C cs 4 an ale am/dm t d(csCwe) t d(csCrde) t h(we Ccs) t h(rdeC cs) address t d(anCwe) t d(anCrde ) t h(rde Can) t w(ale) t d(ale Cwe) address address t su(aCale) t h(ale Ca) t d(aCwe) t d(aCrde) t d(ale Crde) t pxz(rde Cdz) t pzx(rde Cdz) address data address address wel, weh t h(we Can) t d(we Cdq) dm in rde rsmp test conditions ? vcc = 5 v 10% ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v ? data input dm in : v il = 0.8 v, v ih = 2.5 v t su(dCrde) t h(rde Cd) t w(rde) t d(rsmp Cwe) t h( f 1 Crsmp) t d(rsmp Crde) data t d(rdeC f 1 ) t d(weC f 1 ) t d(weC f 1 ) t d(rdeC f 1 )
preliminary notice: this is not a final specification. some parametric limits are subject to change. 30 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs [external bus mode b] memory expansion mode and microprocessor mode (wait 1 : the external area is accessed when wait bit = 0 and wait selection bit = 1.) t c t w(l) t w(h) t f t r t w(ale) t d(anCwe) am/dm address t d(csCrde) t w(rde) t d(rde- f 1 ) x in f 1 address address cs 0 C cs 4 an ale wel, weh dm in rde rsmp t d(weC f 1 ) t d(rdeC f 1 ) t d(csCwe) t d(aleCwe) t h(rdeCan) t su(aCale) t h(aleCa) t d(aCwe) t d(weCdq) t w(we) t d(aCrde) t pzx(rdeCdz) t h(rdeCcs) t h(rdeCd) t su(dCrde) t d(rsmpCwe) t h( f 1 Crsmp) t d(rsmpCrde) test conditions ? vcc = 5 v 10% ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v ? data input dm in : v il = 0.8 v, v ih = 2.5 v data address t h(weCcs) data t d(weC f 1 ) t h(we-an) t d(aleCrde) t d(anCrde) t h(weCdq) address t pxz(rdeCdz)
31 prom version of m37736mhbxxxgp preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736EHBXXXGP m67736ehbgs [external bus mode b] memory expansion mode and microprocessor mode (wait 0 : the external memory area is accessed when wait bit = 0 and wait selection bit = 0.) t c t r t h(aleCa) t d(aleCwe) t d(weCdq) t w(l) t w(h) t f x in 1 address address address address data cs 0 C cs 4 an ale am/dm wel , weh dm in rde rsmp t d(csCwe) t h(weCcs) t d(csCrde) t d(anCwe) t w(ale) t h(weCan) t d(anCrde) t h(rdeCan) t su(aCale) t h(weCdq) t d(aleCrde) t d(aCwe) t w(we) t d(aCrde) t pxz(rdeCdz) t pzx(rdeCdz) t h(rdeCcs) t h(rdeCd) t su(dCrde) t w(rde) t d(rsmpCwe) t h( 1 Crsmp) t d(rsmpCrde) addressdataaddress test conditions ? vcc = 5 v 10% ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v ? data input dm in : v il = 0.8 v, v ih = 2.5 v t d(weC 1 ) t d(rdeC 1 ) t d(rdeC 1 ) t d(weC 1 ) f f f f f f
preliminary notice: this is not a final specification. some parametric limits are subject to change. 32 prom version of m37736mhbxxxgp mitsubishi microcomputers M37736EHBXXXGP m37736ehbgs ? 1997 mitsubishi electric corp. h-lf488-a ki-9703 printed in japan (rod) 2 new publication, effective mar. 1997. specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. package outline
page p9 right column line 2 line 10 rev. rev. no. date 1.00 first edition 970611 2.00 the following are revised: 980731 revision description list M37736EHBXXXGP, m37736ehbgs datasheet (1) revision description previous version the M37736EHBXXXGP has 28 powerful addressing modes. refer to the mitsubishi semiconductors data book single- chip 16-bit microcomputers for the details of each addressing mode. machine instruction list the M37736EHBXXXGP has 103 machine instructions. refer to the mitsubishi semiconductors data book single- chip 16-bit microcomputers for details. revised version the M37736EHBXXXGP has 28 powerful addressing modes. refer to the 7700 family software manual for the details. machine instruction list the M37736EHBXXXGP has 103 machine instructions. refer to the 7700 family software manual for the details. (2) 80p6n mark specification form (2) 100p6s mark specification form

▲Up To Search▲

Price & Availability of M37736EHBXXXGP

	To Download M37736EHBXXXGP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .